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general description the max696/max697 supervisory circuits reduce the complexity and number of components required for power-supply monitoring and battery-control functions in microprocessor (p) systems. these include p reset and backup-battery switchover, watchdog timer, cmos ram write protection, and power-failure warning. the max696/max697 significantly improve system reliability and accuracy compared to that obtained with separate ics or discrete components. the max696 and max697 are supplied in 16-pin pack - ages and perform six functions: 1) a reset output during power-up, power-down, and brownout conditions. the threshold for this lowline reset is adjustable by an external voltagedivider. 2) a reset pulse if the optional watchdog timer has not been toggled within a specified time. 3) individual outputs for low-line and watchdog fault con - ditions. 4) the reset time may be left at its default value of 50ms, or may be varied with an external capacitor or clock pulses. 5) a separate 1.3v threshold detector for power-fail warn - ing, low-battery detection, or to monitor a power supply other than v cc . the max696 also has battery-backup switching for cmos ram, cmos microprocessor, or other lowpower logic. the max697 lacks battery-backup switching, but has write-protection pins ( ce in and ce out) for cmos ram or eprom. in addition, it consumes less than 250 microamperes. applications computers controllers intelligent instruments critical p power monitoring features adjustable low-line monitor and power-down reset power-ok/reset time delay watchdog timer100ms, 1.6s, or adjustable minimum component count 1a standby current battery-backup power switching (max696) on-board gating of chip-enable signals (max697) separate monitor for power-fail or low-battery warning typical operating circuit appears at end of data sheet. pin configurations continued at end of data sheet. ordering information continued at end of data sheet. 19-0829; rev 5; 7/14 devices in pdip and so packages are available in both leaded and lead(pb)-free packaging. specify lead free by adding the + symbol at the end of the part number when ordering. lead free not available for cerdip package. part temp range pin-package max696 c/d 0c to +70c dice max696cpe 0c to +70c 16 pdip max696cwe 0c to +70c 16 wide so max696epe -40c to +85c 16 pdip max696eje -40c to +85c 16 cerdip max696ewe -40c to +85c 16 wide so max696mje -55c to +125c 16 cerdip v out v batt v cc gnd llin 12 3 4 1615 14 13 n.c. batt on pfi wdi 56 7 8 1211 10 9 osc in osc sel pfo low line top view reset reset wdo max696 max696/max697 microprocessor supervisory circuits ordering informationpin conigurations downloaded from: http:///
terminal voltage (with respect to gnd) v cc .......................................................................-0.3v to +6v v batt ............ ................................. ......................-0.3v to +6v all other inputs (note 1).....................-0.3v to (v out + 0.5v) input current v cc ................................................................................200ma v batt ..............................................................................50ma gnd.................................................................................20ma output current v out ....................................................short-circuit protected all other outputs.............................................................20ma rate-of-rise, v batt , v cc ...............................................100v/s operating temperature range c suffix................................................................0c to +70c e suffix.............................................................-40c to +85c m suffix..........................................................-55c to +125c power dissipation (t a = +70c) 16-pin pdip (derated 7mw/c above +70c)..............600mw 16-pin so (derated 7mw/c above +70c).................600mw 16-pin cerdip (derated 10mw/c above +85c)......600mw storage temperature range..............................-65c to +160c lead temperature (soldering, 10s)..................................+300c (v cc = full operating range, v batt = 2.8v, t a = +25c, unless otherwise noted.) note 1: the input voltage limits on pfi and wdi may be exceeded providing the input current is limited to l ess than 10ma. parameter conditions min typ max units operating voltage range t a = full max696 v cc 3.0 5.5 v max696 v batt 2.0 v cc - 0.3v max697 v cc 3.0 5.5 supply current (max697) t a = full 160 300 a battery-backup switching (max696) v out output voltage i out = 1ma, t a = full v cc - 0.3 v cc - 0.1 v i out = 50ma, t a = full v cc - 0.5 v cc - 0.25 v out in battery-backup mode i out = 250a, v cc < (v batt - 0.2v), t a = full v batt - 0.1 v batt - 0.02 v supply current (excludes i out ) i out = 1ma 1.5 4 ma i out = 50ma 2.5 7 supply current in battery-backup mode v cc = 0v, v batt = 2.8v, t a = +25c 0.6 1 a v cc = 0v, v batt = 2.8v, t a = full 10 battery standby leakage current 5.5v > v cc > (v batt + 0.3v) t a = +25c -100 +20 na t a = full -1.00 +0.02 a battery switchover threshold v cc - v batt power-up 70 mv power-down 50 battery switchover hysteresis 20 mv batt on output voltage i sink - 1.6ma 0.4 v batt on output short-circuit current batt on = v out = 2.4v sink current 7 ma batt on = v out , v cc = 0v 0.5 2.5 25.0 a reset and watchdog timer low-line voltage threshold (ll in ) v cc = +5v, +3v; t a = full 1.25 1.30 1.35 v reset timeout delay figure 6, osc sel high, v cc = 5v 35 50 70 ms watchdog timeout period, internal oscillator long period, v cc = 5v 1.00 1.6 2.25 s short period, v cc = 5v 70 100 140 ms max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 2 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics downloaded from: http:///
(v cc = full operating range, v batt = 2.8v, t a = +25c, unless otherwise noted.) note 2: t a = full operating range note 3: wdi is guaranteed to be in the mid-level (inactive) state if wdi is floating and v cc is in the operating voltage range. wdi is internally biased to 38% of v cc with an impedance of approximately 125k. parameter conditions min typ max units watchdog timeout period, external clock long period 4032 4097 clock cycles short period 960 1025 minimum wdi input pulse width v il = 0.4v, v ih = 3.5v, v cc = 5v 200 ns reset and reset output voltage (note 2) i sink = 400a, v cc = 2v, v batt = 0v 0.4 v i sink = 1.6ma, 3v < v cc < 5.5v 0.4 i source = 1a, v cc = 5v 3.5 low line and wdo output voltage i sink = 800a, t a = full 0.4 v i source = 1a, v cc = 5v, t a = full 3.5 output short-circuit current reset , reset, wdo , low line 1 3 25 a wdi input threshold v cc = 5v (note 3) logic-low 0.8 v logic-high (max696) 3.5 logic-high (max697) 3.8 wdi input current v wdi = v out 20 50 a v wdi = 0v -50 -15 power-fail detector pfi input threshold v cc = 3v, 5v 1.2 1.3 1.4 v pfi - ll in threshold difference v cc = 3v, 5v 15 50 mv pfi input current 0.01 25 na ll in input current max697 -25 0.01 +25 na max696 -500 0.01 +25 pfo output voltage i sink = 1.6ma 0.4 v i source = 1a, v cc = 5v 3.5 pfo short-circuit source current v pfi = 0v, v pfo = 0v 1 3 25 a chip-enable gating (max697) ce in thresholds v il 0.8 v v ih , v cc = 5v 3.0 ce in pullup current 3 a ce out output voltage i sink = 1.6ma 0.4 v i source = 800a v cc - 0.5v i source = 1a, v cc = 0v v cc - 0.05v ce propagation delay v cc = 5v 80 150 ns oscillator osc in input current 2 a osc sel input pullup current 5 a osc in frequency range v osc sel = 0v 0 250 khz osc in frequency with external capacitor v osc sel = 0v, c osc = 47pf 4 khz max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 3 electrical characteristics (continued) downloaded from: http:///
(t a = +25c, unless otherwise noted.) max696 supply voltage (v) supply current (ma) v cc mode 5 4 3 0.25 0.50 0.75 1.00 1.25 1.50 0 0.25 0.50 0.75 1.00 1.25 1.500 2 6 supply current as a function of supply voltage supply current (a) battery mode max697 supply voltage (v) supply current (a) 5 4 3 50 100 150 200 250 0 2 6 supply current as a function of supply voltage supply voltage (v) reset timeout delay (ms) 5 4 3 50 100 150 200 250 300 0 2 6 reset timeout delay as a function of supply voltage v cc mode t a = +25c t a = +25c battery mode t a = 25c max696/max697 microprocessor supervisory circuits maxim integrated 4 www.maximintegrated.com typical operating characteristics downloaded from: http:///
pin name function max696 max697 1 v batt backup-battery input. connect to ground if a backup battery is not used. 2 v out the higher of v cc or v batt is internally switched to v out . connect v out to v cc if v out and v batt are not used. 3 3 v cc +5v input 4 5 gnd 0v ground reference for all signals 5 batt on batt on goes high when v out is internally switched to the v batt input. it goes low when v out is internally switched to v cc . the output typically sinks 7ma and can directly drive the base of an external pnp transistor to increase the output current above the 50ma rating of v out . 6 6 low line low line goes low when ll in falls below 1.3v. it returns high as soon as ll in rises above 1.3v. see figure 5. 7 7 osc in osc in sets the reset delay timing and watchdog timeout period when osc sel floats or is driven low. the timing can also be adjusted by connecting an external capacitor to this pin. see figure 7. when osc sel is high, osc in selects between fast and slow watchdog timeout periods 8 8 osc sel when osc sel is unconnected or driven high, the internal oscillator sets the reset time delay and watchdog timeout period. when osc sel is low, the external oscillator input, osc in, is enabled. osc sel has a 3a internal pullup. see table 1. 9 9 pfi pfi is the noninverting input to the power-fail comparator. when pfi is less than 1.3v, pfo goes low. connect pfi to gnd or v out when not used. see figure 1. 10 10 pfo pfo is the output of the power-fail comparator. it goes low when pfi is less than 1.3v. the comparator is turned off and pfo goes low when v cc is below v batt . 11 11 wdi the watchdog input, wdi, is a three-level input. if wdi remains either high or low for longer than the watchdog timeout period, reset pulses low and wdo goes low. the watchdog timer is disabled when wdi is left loating or is driven to mid-supply. the timer resets with each transition at the watchdog timer input. 12 2 n.c. no connection. leave this pin open. 13 4 ll in low-line input. ll in is the cmos input to a comparator whose other input is a precision 1.3v reference. the output is low line and is also connected to the reset pulse generator. see figure 2. 14 14 wdo the watchdog output, wdo , goes low if wdi remains either high or low for longer than the watchdog timeout period. wdo is set high by the next transition at wdi. if wdi is unconnected or at mid-supply, wdo remains high. wdo also goes high when low line goes low. 15 15 reset reset goes low whenever ll in falls below 1.3v or v cc falls below the v batt input voltage. reset remains low for 50ms after ll in goes above 1.3v. reset also goes low for 50ms if the watchdog timer is enabled but not serviced within its timeout period. the reset pulse width can be adjusted as shown in table 1. 16 16 reset reset is an active-high output. it is the inverse of reset . max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 5 pin description downloaded from: http:///
typical applications max696 a typical connection for the max696 is shown in figure 1. cmos ram is powered from v out . v out is internally connected to v cc when power is present, or to v batt when v cc is less than the battery voltage. v out can supply 50ma from v cc , but if more current is required, an external pnp transistor can be added. when v cc is higher than v batt , the batt on output goes low, providing 7ma of base drive for the external transis - tor. when v cc is lower than v batt , an internal 200 mosfet connects the backup battery to v out . the qui - escent current in the battery-backup mode is 1a maxi - mum when v cc is between 0v and (v batt - 700mv). reset output a voltage detector monitors v cc and generates a reset output to hold the microprocessors reset line low when ll in is below 1.3v. an internal monostable holds reset figure 1. max696 typical application pin name function max696 max697 1 test used during maxim manufacture only. always ground this pin. 12 ce out ce out goes low only when ce in is low and ll in is above 1.3v. see figure 5. 13 ce in the input to the ce gating circuit. connect to gnd or v out if not used. 0.1f 0.1f 3 5 2 v out v v batt cc reset reset low line reset ll in pfo wdo batt on cmos ram a0Ca15 microprocessor 1110 15 18 i/o nmi wdi other system reset sources system status indicators audible alarm 14 6 +5v v cc input 19 4 7 8 13 pfignd osc in osc sel no connection reset 3v battery max696 max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 6 pin description (continued) downloaded from: http:///
low for 50ms after ll in rises above 1.3v. this prevents repeated toggling of reset even if the v cc power drops out and recovers with each power line cycle. the crystal oscillator normally used to generate the clock for microprocessors takes several milliseconds to start. since most microprocessors need several clock cycles to reset, reset must be held low until the microprocessor clock oscillator has started. the power-up reset pulse lasts 50ms to allow for this oscillator startup time. an inverted, active-high reset output is also supplied. power-fail detector the max696 issues a nonmaskable interrupt (nmi) to the microprocessor when a power failure occurs. the power line is monitored by two external resistors connected to the power-fail input (pfi). when the voltage at pfi falls below 1.3v, the power-fail output ( pfo ) drives the processors nmi input low. an earlier power-fail warning can be gener - ated if the unregulated dc input of the regulator is available for monitoring. watchdog timer the microprocessor drives the watchdog input (wdi) with an i/o line. when osc in and osc sel are uncon - nected, the microprocessor must toggle the wdi pin once every 1.6 seconds to verify proper software execution. if a hardware or software failure occurs so that wdi is not toggled, the max696 will issue a 50ms reset pulse after 1.6 seconds. this typically restarts the microprocessors power-up routine. a new reset pulse is issued every 1.6 seconds until wdi is again strobed. the watchdog output ( wdo ) goes low if the watchdog timer is not serviced within its timeout period. once wdo goes low, it remains low until a transition occurs at wdi while reset is high. the watchdog timer feature can be disabled by leaving wdi unconnected. osc in and osc sel also allow other watchdog timing options, as shown in table 1 and figure 7. figure 2. max696/max697 block diagram + - + - + - batt on (max696) v out (max696) v batt (max696) v cc chip-enable output (max697) low line reset reset watchdog output power-fail output 2 12 6 1516 1410 watchdog timer ground 4 1.30v power-fail input watchdog transition detector timebase for reset and watchdog reset generator watchdog input 9 11 8 7 ll in osc in osc sel (max697) chip-enable input 13 3 1 5 max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 7 downloaded from: http:///
max697 the max697 is nearly identical to the max696. the max697 lacks the battery-backup feature, so it does not have the v batt , v out , or batt on pins. this allows the max697 to consume less than 250 microamperes, and it allows the inclusion of ram write-protection pins. see figure 2. detailed description battery switchover and v out (max696) battery switchover and v out (max696) the battery- switchover circuit compares v cc to the v batt input, and connects v out to whichever is higher. switchover occurs when v cc is 50mv greater than v batt as v cc falls, and when v cc is 70mv more than v batt as v cc rises (see figure 3). the switchover comparator has 20mv of hys - teresis to prevent repeated, rapid switching if v cc falls very slowly or remains nearly equal to the battery voltage. when v cc is higher than v batt , v cc is internally switched to v out with a low-saturation pnp transistor. v out has 50ma output current capability. use an external pnp pass transistor in parallel with the internal transistor if the output current requirement at v out exceeds 50ma or if a lower v cc - v out voltage differential is desired. the batt on output can directly drive the base of the external transistor. it should be noted that the max696 need only supply the average current drawn by the cmos ram if there is adequate filtering. many ram data sheets specify a 75ma maximum supply current, but this peak current spike lasts only 100ns. a 0.1f bypass capacitor at v out supplies the high instantaneous current, while v out need only supply the average load current, which is much less. a capacitance of 0.1f or greater must be connected to the v out terminal to ensure stability. a 200 mosfet connects the v batt input to v out during battery backup. this mosfet has very low input- to-output differential (dropout voltage) at the low current levels required for battery backup of cmos ram or other low-power cmos circuitry. when v cc equals v batt , the supply current is typically 12a. when v cc is between 0v and (v batt - 700mv), the typical supply current is only 600na (typ), 1a (max). figure 3. max696 battery-switchover block diagram + - + - p 700mv 100mv 3v battery input base drive v cc 0.1f to cmos ram and real-time clock v cc in batt on p-channel mosfet internalshutdown signal when v batt > v cc + 0.7v low iq mode select v out v cc +5v v batt max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 8 downloaded from: http:///
the max696 operates with battery voltages from 2.0v to 4.25v. the battery voltage should not be within 0.5v of v cc , or switchover may occur. high-value capacitors, either standard electrolytic or the farad-size double- layer capacitors, can also be used for short-term memory backup. the capacitor charging voltage should include a diode to limit the fully charged voltage to approximately 0.5v less than v cc . the charging resistor for recharge - able batteries should be connected to v out since this eliminates the discharge path that exists if the resistor is connected to v cc . a small leakage current of typically 10na (20na max) flows out of the v batt terminal. this current varies with the amount of current that is drawn from v out , but its polarity is such that the backup battery is always slightly charged, and is never discharged while v cc is in its operating voltage range. this extends the shelf life of the backup battery by compensating for its self-discharge cur - rent. also note that this current poses no problem when lithium batteries are used for backup since the maximum current (20na) is safe for even the smallest lithium cells. if the battery-switchover section is not used, connect v batt to gnd and connect v out to v cc . table 2 shows the state of the inputs and output in the lowpower battery- backup mode. reset output reset is an active-low output that goes low whenever ll in falls below 1.3v. it remains low until ll in rises above 1.312v for 50ms. (see figures 4 and 5.) the guaranteed minimum and maximum low-line thresh - olds of the max696/max697 are 1.25v and 1.35v. the ll in comparator has approximately 12mv of hysteresis. the response time of the reset voltage comparator is about 100s. ll in should be bypassed to ensure that glitches do not activate the reset output. reset also goes low if the watchdog timer is enabled and wdi remains either high or low longer than the watchdog timeout period. reset has an internal 3a pullup, and can either connect to an open-collector reset bus or direct - ly drive a cmos gate without an external pullup resistor. figure 4. reset block diagram (max697) ce in ce out (max697) low line v cc ll in watchdog from watchdog timer 10khz clock from timebase section reset reset time q n + - power-on reset reset reset 1.3v max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 9 downloaded from: http:///
ce gating and ram write protection the max697 uses two pins to control the ce or write inputs of cmos rams. when ll in is > 1.3v, ce out is a buffered replica of ce in, with a 50ns propagation delay. if ll in input falls below 1.3v (1.2v min, 1.4v max), an internal gate forces ce out high, independent of ce in. the ce output is also forced high when v cc is less than v batt . (see figure 4.) ce out typically drives the ce , cs , or write input of battery backed up cmos ram. this ensures the integrity of the data in memory by preventing write operations when v cc is at an invalid level. similar protection of eeproms can be achieved by using the ce out to drive the store or write inputs of an eeprom, earom, or novram. if the 50ns typical propagation delay of ce out is too long, connect ce in to gnd and use the resulting ce out to control a high-speed external logic gate. a second alternative is to and the low line output with the ce or wr signal. an external logic gate and the reset output of the max696/max697 can also be used for cmos ram write protection. 1.25v comparator and power-fail warning the power-fail input (pfi) is compared to an internal 1.3v reference. the power-fail output ( pfo ) goes low when the voltage at pfi is less than 1.3v. typically pfi is driven bay an external voltage-divider that senses either the unregu - lated dc input to the systems v cc regulator or the regu - lated output. the voltage-divider ration can be chosen so the voltage at pfi falls below 1.3v several milliseconds before the ll in falls below 1.3v. pfo is normally used to interrupt the microprocessor so that data can be stored in ram before ll in falls below 1.3v and the reset output goes low. the power-fail detector can also monitor the backup bat - tery to warn of a low-battery condition. to conserve bat - tery power, the power-fail detector comparator is turned off and pfo is forced low when v cc is lower than the v batt input voltage. watchdog timer and oscillator the watchdog circuit monitors the activity of the micropro - cessor. if the microprocessor does not toggle the watch - dog input (wdi) within the selected timeout period, a 50ms reset pulse is generated. since many systems cannot service the watchdog timer immediately after a reset, the max696/max697 have a longer timeout period after figure 5. max697 reset timing ll in 1.312v 1.3v 1.312v 1.3v 50ms 50ms low line output (max697) ce in (max697) ce out reset output max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 10 downloaded from: http:///
a reset is issued. the normal timeout period becomes effective following the first transition of wdi after reset has gone high. the watchdog timer is restarted at the end of reset, whether the reset was caused by lack of activ - ity on wdi or by ll in falling below 1.3v. if wdi remains either high or low, reset pulses will be issued every 1.6s. the watchdog monitor can be deactivated by floating the watchdog input (wdi). the watchdog output ( wdo ) goes low if the watchdog timer times out, and it remains low until set high by the next transition on the watchdog input. wdo is also set high when ll in goes below 1.3v. the watchdog timeout period defaults to 1.6s and the reset pulse width defaults to 50ms. the max696 and max697 allow these times to be adjusted per table 1. the internal oscillator is enabled when osc sel is high or floating. in this mode, osc in selects between the 1.6s and 100ms watchdog timeout periods. in either case, immediately after a reset, the timeout period is 1.6s. this gives the microprocessor time to reinitialize the system. wd transmissions while reset is low are ignored. if osc in is low, then the 100ms watchdog period becomes effec - tive after the first transition of wdi. the software should be written so the i/o port driving wdi is left in its power-up reset state until the initialization routines are completed and the microprocessor is able to toggle wdi at the mini - mum 70ms watchdog timeout period. figure 6. watchdog timer block diagram watchdog timeout selector logic watchdog counter prescaler reset counter q6 q11 q13q15 r r q10/12 watchdog fault ff long/ short ff reset flip flop r q q q 10.24khz from internal oscillator or externally set frequency from osc in pin s r s r s q low line goes high at the end of watchdog timeout period reset reset transition detector low line (hi if ll in < 1.3v) for each transition + - + - v cc 1.0v 2.7v watchdog input hi if watchdog input is floating watchdog timeout select watchdog output max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 11 downloaded from: http:///
applications information adding hysteresis to the power-fail comparator since the power-fail comparator circuit is noninvert - ing, hysteresis can be added by connecting a resistor between the pfo output and the pfi input as shown in figure 7. when pfo is low, resistor r3 sinks current from the summing junction at the pfi pin. when pfo is high, the series combination of r3 and r4 source current into the pfi summing junction. alternate watchdog input drive circuits the watchdog feature can be enabled and disabled under program control by driving wdi with a three-state buffer (figure 8). the drawback to this circuit is that a software fault may erroneously three-state the buffer, thereby preventing the max696/max697 from detecting that the microprocessor is no longer working. in most cases, a better method is to extend the watchdog period rather than disabling the watchdog. see figure 9. when the control input is high, the osc sel pin is low and the watchdog timeout is set by the external capacitor. a 0.01f capacitor sets a watchdog timeout delay of 100s. when the control input is low, the osc sel pin is driven high, selecting the internal oscillator. the 100ms or the 1.6s period is chosen, depending on which diode in figure 9 is used. figure 7. adding hysteresis to the power-fail voltage comparator figure 8. disabling the watchdog under program control figure 9. selecting internal or external watchdog timeout v cc pfo pfi gnd 7805 7v - 15v +5v r175k ? r410k ? r213k ? r3300k ? top v h = 9.125v v l = 7.9v hysteresis = 1.23v v h = 1.3v v l = 1.3v { } 1 + + r1r2 r1r3 { } 1 + + r1r2 (5v - 1.3v) r1 1.3v (r3 + r4) hysteresis 5v x r1r3 assuming r4 << r3 max696max697 wdi gnd +5v watchdog strobe watchdog disable en v cc max696max697 osc sel osc in gnd +5v v cc low = internal watchdog timeout hi = external watchdog timeout connect for 100ms timeout when internal timeout is selected connect for 1.6s internal timeout max696max697 max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 12 downloaded from: http:///
table 1. max696 and max697 reset pulse width and watchdog timeout selections (notes 1, 2) table 2. input and output status in battery-backup mode osc sel (note 3) osc in watchdog timeout period reset timeout period normal immediately after reset low external clock input 1024 clocks 4096 clocks 512 clocks low external capacitor 400ms/47pf x c 1.6s/47pf x c 200ms/47pf x c high/floating low 100ms 1.6s 50ms high/floating floating 1.6s 1.6s 50ms i/o status v batt , v out v batt is connected to v out with an internal mosfet (max696 only). reset logic-low. reset logic-high. the open-circuit output voltage is equal to v out . low line logic-low. batt on logic-high (max696 only). wdi wdi is internally disconnected from its internal pullup and does not source or sink current as long as its input voltage is between gnd and v out . the input voltage does not affect supply current. wdo logic-high. pfi the power-fail comparator is turned off and the power-fail input voltage has no effect on the pow er-fail output. pfo logic-low. ce in ce in is internally disconnected from its internal pullup and does not source or sink current as long as its input voltage is between gnd and v out . the input voltage does not affect supply current (max696 only). ce out logic-high (max697 only). osc in osc in is ignored. osc sel osc sel is ignored. v cc approximately 12a is drawn from the v batt input when v cc is between (v batt + 100mv) and (v batt - 700mv). the supply current is 1a maximum when v cc is less than v batt - 700mv. note 1: when the max696/max697 osc sel pin is low, osc in can be driven by an external clock signal, or an external capacitor can be connected between osc in and gnd. the nominal internal oscillator frequency is 10.2 4khz. the nominal oscillator frequency with external capacitor is f osc (hz) = 184,000/c osc (pf). note 2: see the electrical characteristics table for minimum and maximum timing values. note 3: high for the osc sel pin should be connected to v out , not v cc (on the max696). max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 13 downloaded from: http:///
devices in pdip and so packages are available in both leaded and lead(pb)-free packaging. specify lead free by adding the + symbol at the end of the part number when ordering. lead free not available for cerdip package. part temp range pin-package max697 c/d 0c to +70c dice max697cpe 0c to +70c 16 pdip max697cwe 0c to +70c 16 wide so max697epe -40c to +85c 16 pdip max697eje -40c to +85c 16 cerdip max697ewe -40c to +85c 16 wide so max697mje -55c to +125c 16 cerdip power tocmos ram p power p system v out v batt v cc p reset reset ll in pfo wdi i/oline p nmi -5v pfi gnd reset max696 ce in v cc llin n.c. reset reset test wdo 12 3 4 1615 14 13 gnd low line osc sel osc in pfi wdi 56 7 8 1211 10 9 top view pfo ce out max697 max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 14 typical operating circuit ordering information pin conigurat ions (cont inued) downloaded from: http:///
package type package code outline no. land pattern no. 16 cerdip j16-3 21-0045 16 pdip p16+1 21-0043 16 wide so w16+1 21-0042 90-0107 v cc v cc ll in ll in gnd gnd batt on test reset reset v batt v out reset reset wdo wdo low line osc in osc sel pfi pfo low line osc in osc sel pfi pfo wdi wdi ce in ce out max697 max696 0.084 [2.13mm] 0.116 [2.95mm] 0.084 [2.13mm] 0.116 [2.95mm] max696/max697 microprocessor supervisory circuits www.maximintegrated.com maxim integrated 15 chip topography package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. downloaded from: http:///
revision number revision date description pages changed 4 5/14 no /v opns; removed automotive reference from applications section 1 5 7/14 corrected typos in figures 4, 5; updated reset output section 9, 10 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max696/max697 microprocessor supervisory circuits ? 2014 maxim integrated products, inc. 16 revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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